Реферат: Микроконтроллер 8250

Bit 2 - transmit FIFO reset

Bit 3 - DMA mode select

Bit 4 - reserved

Bit 5 - reserved

Bit 6 - receiver trigger (LSB)

Bit 7 - receiver trigger (MSB)

Bit 0 - Set to 1 to enable both receive and transmit FIFOs. This bit must be set when any other bits are set.

Bit 1 - Set to 1 to clear the receiver FIFO. (flush the queue). This bit automatically resets to 0.

Bit 2 - Set to 1 to clear the t