Реферат: VHDL - технології дослідження цифрових пристроїв

Y1 : out STD_LOGIC;

Y2 : out STD_LOGIC;

Y3 : out STD_LOGIC;

Y4 : out STD_LOGIC

);

end Counter;

architecture Counter of Counter is

---- Component declarations -----

component D_trig

port (

c : in STD_LOGIC;

d : in STD_LOGIC;

nr : in STD_LOGIC;

ns : in STD_LOGIC;

N : out STD_LOGIC;

NQ : out STD_LOGIC

);

end component;

--- Signal declarations used on the diagram ----

signal NET250 : STD_LOGIC;

signal NET260 : STD_LOGIC;

signal NET335 : STD_LOGIC;

signal NET346 : STD_LOGIC;

signal NET420 : STD_LOGIC;

signal NET436 : STD_LOGIC;

begin

---- Component instantiations ----

U1 : D_trig

port map(