Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

Adr: out std_logic_vector (5 downto 0);

Instr0: out std_logic;

Instr1: out std_logic;

Instr2: out std_logic;

PCIn: out std_logic;

IncPC: out std_logic;

IrIn: out std_logic;

MarIn:out std_logic;

RdWr:out std_logic;

CS:out std_logic;

MbrIn:out std_logic;

MbrOut:out std_logic;

MbrInD:out std_logic;

MbrOutD:out std_logic;

RzIn:out std_logic;

RzOut:out std_logic;

Inv:out std_logic;

RAIn:out std_logic;

RIn:out std_logic;

ROut:out std_logic;

RDCIn:out std_logic;

SADD:out std_logic;

InvZ: out std_logic);

end CBR;

architecture CBR of CBR is

begin

process(CbrIN)

begin

if CbrIN='1' and CbrIN'event then