Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

Instr1<=InstrCom(1) after 1ns;

Instr2<=InstrCom(0) after 1ns;

ADR<=InstrCom (3 to 8) after 1ns;

PCIn <=InstrCom(9) after 1ns;

IncPC<=InstrCom(10) after 1ns;

IrIn <=InstrCom(11) after 1ns;

MarIn <=InstrCom(12) after 1ns;

RdWr <=InstrCom(13) after 1ns;

CS <=InstrCom(14) after 1ns;

MbrIn<=InstrCom(15) after 1ns;

MbrOut<=InstrCom(16) after 1ns;

MbrInD<=InstrCom(17) after 1ns;

MbrOutD<=InstrCom(18) after 1ns;

RzIn <=InstrCom(19) after 1ns;

RzOut<=InstrCom(20) after 1ns;

Inv<=InstrCom(21) after 1ns;

RAIn<=InstrCom(22) after 1ns;

RIn <=InstrCom(23) after 1ns;

ROut<=InstrCom(24) after 1ns;

RDCIn <=InstrCom(25) after 1ns;

SADD<=InstrCom(26) after 1ns;

InvZ<=InstrCom(27) after 1ns;

end if;

end process;

end CBR;

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library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity IR is