Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

port (in1: in std_logic;

in2: in std_logic;

Sout: out std_logic);

end LogAnd;

architecture LogAnd of LogAnd is

begin

Sout<=in1 and in2 after 1ns;

end LogAnd;

–

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity LogOR is

port (in1: in std_logic;

in2: in std_logic;

SOut: out std_logic);

end LogOR;

architecture LogOR of LogOR is

begin

SOut<=in1 or in2 after 1ns;

end LogOR;

–

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity MUX is

port (IN1: in std_logic_vector (5 downto 0);

IN2: in std_logic_vector (5 downto 0);

IN3: in std_logic_vector (5 downto 0);

Adr0: in std_logic;

Adr1: in std_logic;