Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

signal reg: std_logic_vector (7 downto 0):= «00000000»;

begin

process (CLK, RST)

begin

if CLK='0' and CLK'event and MarIn='1' then reg<=AdrIn;

end if;

if CLK='1' and CLK'event then AdrOut<=reg;

end if;

if RST='1' then reg<= «00000000»;

end if;

end process;

end MAR;

–

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity MBR is

port (RST: in std_logic;

CLK: in std_logic;

MbrIn: in std_logic;

MbrOut: in std_logic;

MbrInD: in std_logic;

MbrOutD: in std_logic;

DataIn: inout std_logic_vector (7 downto 0);

DataOut: inout std_logic_vector (7 downto 0));

end MBR;

architecture MBR of MBR is

signal reg: std_logic_vector (7 downto 0);

begin

Process (CLK, RST)