Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

SIn: in std_logic_vector (5 downto 0);

SOut: out std_logic_vector (5 downto 0));

end component;

–

component ALU

port (A: in std_logic_vector (7 downto 0);

B: in std_logic_vector (7 downto 0);

CLK: in std_logic;

SADD: in std_logic;

FC: out std_logic;

FZ: out std_logic;

Q: out std_logic_vector (7 downto 0));

end component;

–

component CAR

port (CarIn: in std_logic;

D: in std_logic_vector (5 downto 0);

CarOut: out STD_LOGIC;

Q: out std_logic_vector (5 downto 0));

end component;

–

component CBR

port (CbrIn: in std_logic;

InstrCom: in std_logic_vector (0 to 27);

Adr: out std_logic_vector (5 downto 0);

CS: out STD_LOGIC;

IncPC: out STD_LOGIC;

Instr0: out std_logic;

Instr1: out std_logic;