Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

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component IR

port (Command: in std_logic_vector (7 downto 0);

IRin: in std_logic;

Reset: in std_logic;

Com: out std_logic_vector (7 downto 0);

IrOut: out STD_LOGIC);

end component;

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component LogAnd

port (in1: in std_logic;

in2: in std_logic;

Sout: out std_logic);

end component;

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component LogOR

port (in1: in std_logic;

in2: in std_logic;

SOut: out std_logic);

end component;

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component MAR

port (AdrIn: in std_logic_vector (7 downto 0);

CLK: in std_logic;

MarIn: in std_logic;

RST: in std_logic;

AdrOut: out std_logic_vector (7 downto 0));

end component;

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