Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

CLK: in STD_LOGIC;

IncPC: in STD_LOGIC;

PCIn: in STD_LOGIC;

RST: in STD_LOGIC;

AdrOut: out STD_LOGIC_VECTOR (7 downto 0));

end component;

–

component R0

port (C: in STD_LOGIC;

CLK: in std_logic;

DataIn: in std_logic_vector (7 downto 0);

RIn: in std_logic;

ROut: in std_logic;

RST: in std_logic;

DataOut: out std_logic_vector (7 downto 0));

end component;

–

component RA

port (

CLK: in STD_LOGIC;

DIn: in std_logic_vector (7 downto 0);

RAIn: in std_logic;

DOut: out std_logic_vector (7 downto 0));

end component;

–

component RAM

port (Adr: in STD_LOGIC_VECTOR (7 downto 0);

CS: in STD_LOGIC;

RdWr: in STD_LOGIC;