Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

end component;

–

component RDC

port (Number: in std_logic_vector (7 downto 0);

RDCIn: in std_logic;

R1: out std_logic;

R2: out std_logic;

R3: out std_logic;

R4: out std_logic);

end component;

–

component RZ

port (CLK: in STD_LOGIC;

DIn: in STD_LOGIC_VECTOR (7 downto 0);

InvZ: in STD_LOGIC;

RST: in STD_LOGIC;

RZIn: in STD_LOGIC;

RZOut: in STD_LOGIC;

DOut: out STD_LOGIC_VECTOR (7 downto 0));

end component;

–

component R_1bit is

port (reg_in, IE: in std_logic;

CLK, Zero:in std_logic;

reg_out: out std_logic);

end component;

–

signal CS, IncPC, IrIn, MarIn, MbrIn, MbrOut, JB: STD_LOGIC;

signal S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, SR1, SR2, SR3, SR4: STD_LOGIC;