Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

signal PCIN, RaIn, RDCIn, RdWr, RIn, ROut, RzIn, RzOut, SADD: STD_LOGIC;

signal Adr: std_logic_vector (7 downto 0);

signal BUS2, BUS6, BUS7, BUS8, BUS11: std_logic_vector (5 downto 0);

signal BUS10: std_logic_vector (27 downto 0);

signal BUS0, BUS1, BUS3, BUS4, BUS5: std_logic_vector (7 downto 0);

signal MemOut: STD_LOGIC_VECTOR (7 downto 0);

–

begin

DD0: IR port map (Com => BUS1, Command => DataBus, IRin => IrIn, IrOut => S3,

Reset => Reset);

DD1: LogAnd port map (Sout => S5, in1 => bit_outs, in2 =>S4);

DD2: MAR port map (AdrIn => BUS0, AdrOut => Adr, CLK => CLK, MarIn => MarIn,

RST => Reset);

DD3: RAM port map (Adr => Adr, CS => CS, Data => MemOut, RdWr => RdWr);

DD4: MBR port map (CLK => CLK, DataIn => MemOut, DataOut => DataBus,

MbrIn => MbrIn, MbrInD => S6, MbrOut => MbrOut,

MbrOutD => S7, RST => Reset);

DD5: R0 port map (C => SR1, CLK => CLK, DataIn => DataBus, DataOut => DataBus,

RIn => RIn, ROut => ROut, RST => Reset);

DD6: R0 port map (C => SR2, CLK => CLK, DataIn => DataBus, DataOut => DataBus,

RIn => RIn, ROut => ROut, RST => Reset);

DD7: R0 port map (C => SR3, CLK => CLK, DataIn => DataBus, DataOut => DataBus,

RIn => RIn, ROut => ROut, RST => Reset);

DD8: R0 port map (C => SR4, CLK => CLK, DataIn => DataBus, DataOut => DataBus,

RIn => RIn, ROut => ROut, RST => Reset);

DD9: RA port map (CLK => CLK, DIn => DataBus, DOut => BUS3, RAIn => RaIn);

DD10: ALU port map (A => BUS4, B => DataBus, CLK => CLK, FC => FC_sig, FZ => S1,

Q => BUS5, SADD => SADD);

DD11: DC1 port map (Ale => S3, Com => BUS1, ComAdr => BUS2);