Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

port (CLK: in STD_LOGIC;

MbrIn: in STD_LOGIC;

MbrInD: in STD_LOGIC;

MbrOut: in STD_LOGIC;

MbrOutD: in STD_LOGIC;

RST: in STD_LOGIC;

DataIn: inout STD_LOGIC_VECTOR (7 downto 0);

DataOut: inout STD_LOGIC_VECTOR (7 downto 0));

end component;

–

component Memory

port (Adr: in std_logic_vector (5 downto 0);

RD: in std_logic;

InstrCom: out std_logic_vector (0 to 27);

MrOut: out STD_LOGIC);

end component;

–

component MUX

port (Adr0: in std_logic;

Adr1: in std_logic;

CLK: in STD_LOGIC;

IN1: in std_logic_vector (5 downto 0);

IN2: in std_logic_vector (5 downto 0);

IN3: in std_logic_vector (5 downto 0);

MuxOut: out STD_LOGIC;

OUT1: out std_logic_vector (5 downto 0));

end component;

–

component PC