Курсовая работа: Моделирование процессора (операционного и управляющего автоматов) для выполнения набора машинных команд

Inv: out STD_LOGIC;

InvZ: out STD_LOGIC;

IrIn: out std_logic;

MarIn: out STD_LOGIC;

MbrIn: out STD_LOGIC;

MbrInD: out STD_LOGIC;

MbrOut: out STD_LOGIC;

MbrOutD: out STD_LOGIC;

PCin: out STD_LOGIC;

RAIn: out STD_LOGIC;

RDCIn: out STD_LOGIC;

RIn: out STD_LOGIC;

ROut: out STD_LOGIC;

RdWr: out STD_LOGIC;

RzIn: out STD_LOGIC;

RzOut: out STD_LOGIC;

SADD: out STD_LOGIC);

end component;

–

component DC1

port (Ale: in STD_LOGIC;

Com: in std_logic_vector (7 downto 0);

ComAdr: out std_logic_vector (5 downto 0));

end component;

–

component INV

port (DIn: in std_logic_vector (7 downto 0);

Inv: in std_logic;

DOut: out std_logic_vector (7 downto 0));