Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

------------------------------------------------------------

component MBR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EO: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

-------------------------------------------------------------

component PC is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

Inc: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

--------------------------------------------------------------

component ALU is

port(In1: in std_logic_vector(7 downto 0);

OP: in std_logic;

Res: out std_logic_vector(7 downto 0);

RST: in std_logic;

Clk: in std_logic);