Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

rd: in std_logic;

ld: in std_logic);

end Memory;

architecture Memory of Memory is

type t_rom_data is array (15 downto 0) of std_logic_vector(7 downto 0);

type rom_file_type is file of character;

file rom_file: rom_file_type;

signal rom_data: t_rom_data;

begin

process(addr,rd)

variable i: natural;

begin

if rd = '1' then

i := conv_integer(addr);

data <= rom_data(i) after 5ns;

else

data <= (others => 'Z');

end if;

end process;

process(ld)

variable c: character;

begin

if ld='1' then file_open(rom_file,file_name,read_mode);

for i in 0 to 15 loop

for b in 7 downto 0 loop

c:='U';

if not(endfile(rom_file)) then read(rom_file,c);

while not(endfile(rom_file)) and c/='0' and c/='1' and c/='Z' and c/='W'

and c/='L' and c/='H' and c/='-' and c/='X' and c/='U' loop