Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

RST: in std_logic;

Clk: in std_logic);

end BlockRG;

architecture BlockRG of BlockRG is

signal Enable: std_logic_vector(3 downto 0);

component REGI is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component REGI;

component MUX is

port(D: in std_logic_vector(1 downto 0);

P: in std_logic;

Q: out std_logic_vector(3 downto 0));

end component MUX;

begin

Registers: for i in 3 downto 0 generate

Reg: REGI port map(D=>D,Q=>open,EI=>Enable(i),RST=>RST,Clk=>Clk);

end generate;

Switch: MUX port map(D=>Addr,P=>EI,Q=>Enable);

end BlockRG;

Описание узла АЛУ:

library ieee;

use ieee.std_logic_1164.all;

entity ALU is

port(In1: in std_logic_vector(7 downto 0);

OP: in std_logic;