Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

library ieee;

use ieee.std_logic_1164.all;

entity MBR is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EO: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end MBR;

architecture MBR of MBR is

signal master, slave: std_logic_vector(7 downto 0);

begin

process(D,RST,Clk)

begin

if Clk='0'then

if RST='1' then master<=(others => '0') after 2ns;

else master<=D after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1'then slave<=master after 2ns;

end if;

end process;

process(slave,EO)

begin

if EO='1'then Q<=slave;

else Q<=(others => 'Z');