Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

end architecture MAR;

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library ieee;

use ieee.std_logic_1164.all;

entity REGI is

port(D: in std_logic_vector(7 downto 0);

Q: out std_logic_vector(7 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end REGI;

architecture REGI of REGI is

signal master, slave: std_logic_vector(7 downto 0);

begin

Q<=slave;

process(D,RST,Clk,EI)

begin

if Clk='0'then

if RST='1' then master<=(others => '0') after 2ns;

elsif EI='1' then master<=D after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1'then slave<=master after 2ns;

end if;

end process;

end architecture REGI;