Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

end process;

end PC;

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Decoder is

generic(n: integer:=2);

port(D: in std_logic_vector(n-1 downto 0);

Q: out std_logic_vector((2**n)-1 downto 0));

end Decoder;

architecture Decoder of Decoder is

begin

process(D)

variable i:integer;

variable s:bit_vector((2**n)-1 downto 0);

begin

s:=(0 => '1', others => '0');

i:=conv_integer(D);

s:=s rol i;

for ind in 2**n-1 downto 0 loop

if s(ind)='0' then Q(ind)<='0' after 2ns;

else Q(ind)<='1' after 2ns;

end if;

end loop;

end process;

end architecture;

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library ieee;