Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

use ieee.std_logic_unsigned.all;

entity MUX is

port(D: in std_logic_vector(1 downto 0);

P: in std_logic;

Q: out std_logic_vector(3 downto 0));

end MUX;

architecture MUX of MUX is

begin

process(D,P)

variable i:integer;

variable s:bit_vector(3 downto 0);

begin

s:=(0 => '1', others => '0');

i:=conv_integer(D);

s:=s rol i;

for ind in 3 downto 0 loop

if s(ind)='0' then Q(ind)<='0' after 2ns;

else Q(ind)<=P after 2ns;

end if;

end loop;

end process;

end architecture MUX;

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Описание блока РОН:

library ieee;

use ieee.std_logic_1164.all;

entity BlockRG is

port(D: in std_logic_vector(7 downto 0);

Addr: in std_logic_vector(1 downto 0);