Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

end process;

end architecture MBR;

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Counter is

port(Q: out std_logic_vector(2 downto 0);

RST: in std_logic;

Clk: in std_logic);

end Counter;

architecture Counter of Counter is

signal master, slave, slave_inc: std_logic_vector(2 downto 0);

begin

Q<=slave;

slave_inc<=slave+1 after 2ns;

process(slave_inc,RST,Clk)

begin

if Clk='0'then

if RST='1'then master<=(others => '0') after 2ns;

else master<=slave_inc after 2ns;

end if;

end if;

end process;

process(master,Clk)

begin

if Clk='1' then slave<=master after 2ns;

end if;

end process;