Курсовая работа: Разработка структуры процессора на основе МПА с жесткой логикой

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component BlockRG is

port(D: in std_logic_vector(7 downto 0);

Addr: in std_logic_vector(1 downto 0);

EI: in std_logic;

RST: in std_logic;

Clk: in std_logic);

end component;

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component Memory is

generic(file_name: string:= "MEM.DAT");

port (addr: in std_logic_vector(7 downto 0);

data: out std_logic_vector(7 downto 0);

rd: in std_logic;

ld: in std_logic);

end component;

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component CU is

port(Instr: in std_logic_vector(1 downto 0);

AccIn: out std_logic;

ALURL: out std_logic;

RegIn: out std_logic;

PCIn: out std_logic;

PCInc: out std_logic;

MBROut: out std_logic;

IRIn: out std_logic;

MEMRd: out std_logic;

Reset: inout std_logic;

RST: in std_logic;