Курсовая работа: Синтез схеми ПЛІС для інвертора

SIGNAL sel_data_ram: STD_LOGIC;-- 1 when accessing R0-R15

SIGNAL jump_pc: STD_LOGIC; -- 1 when overwriting PC

SIGNAL inc_pc: STD_LOGIC; -- 1 when incrementing PC

SIGNAL ld_ir: STD_LOGIC; -- 1 when loading IR

SIGNAL ld_ir_lsn: STD_LOGIC;-- 1 when loading LSN of IR

-- ALU operation code possible ALU opcodes

SIGNAL alu_op: STD_LOGIC_VECTOR (2 DOWNTO 0);

--pass input to output

CONSTANT PASS_OP: STD_LOGIC_VECTOR (2 DOWNTO 0):= "001";

CONSTANT ADD_OP: STD_LOGIC_VECTOR (2 DOWNTO 0):= "010"; -- add inputs

CONSTANT XOR_OP: STD_LOGIC_VECTOR (2 DOWNTO 0):= "011"; -- XOR inputs

CONSTANT AND_OP: STD_LOGIC_VECTOR (2 DOWNTO 0):= "100"; -- test input for 0

CONSTANT SET_CARRY_OP: STD_LOGIC_VECTOR (2 DOWNTO 0) := "101"; --set carry

CONSTANT CLR_CARRY_OP: STD_LOGIC_VECTOR (2 DOWNTO 0) := "110"; --clear carry

-- current and next instruction register

SIGNAL curr_ir, next_ir: STD_LOGIC_VECTOR (7 DOWNTO 0);

-- possible instruction opcodes

CONSTANT CLEAR_C: STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";

CONSTANT SET_C: STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000001";

CONSTANT SKIP_C: STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000010";

CONSTANT SKIP_Z: STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000011";

CONSTANT LOAD_IMM: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";

CONSTANT ADD_IMM: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0010";

CONSTANT STORE_DIR:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0011";

CONSTANT LOAD_DIR: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0100";

CONSTANT ADD_DIR: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0101";

CONSTANT XOR_DIR: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110";

CONSTANT TEST_DIR: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0111";

CONSTANT JUMP: STD_LOGIC := '1';