Курсовая работа: Синтез схеми ПЛІС для інвертора

carry_out <= curr_carry;

pc_out <= curr_pc;

acc_out <= curr_acc;

ir_out <= curr_ir;

sel_ram <= sel_data_ram;

-- external RAM control signals

oeb <= NOT(read);-- enable RAM drivers during RAM read operations

web <= NOT(write);-- RAM write line (in last half of clock)

-- address either the data or program sections of the external RAM

address <= "000" &amp; curr_ir(3 DOWNTO 0) WHEN sel_data_ram='1' ELSE

curr_pc;

-- drive the accumulator contents into the RAM during write operations

-- but disable the drivers into high-impedance state at all other times

data <= "0000" &amp; curr_acc WHEN write='1' ELSE "ZZZZZZZZ";

-- load the instruction register with a new opcode

next_ir <= data WHEN ld_ir='1' ELSE

-- or load only the lower 4 bits of the IR with data

curr_ir(7 DOWNTO 4) &amp; data(3 DOWNTO 0) WHEN ld_ir_lsn='1' ELSE

-- or else don't change the IR

curr_ir;

-- load the PC with an address to jump to

next_pc <= curr_ir(6 DOWNTO 0) WHEN jump_pc='1' ELSE

-- or increment the PC

curr_pc+1 WHEN inc_pc='1' ELSE

-- or else don't change the PC

curr_pc;

-- this process describes the operations of the ALU

PROCESS (alu_op,curr_zero,curr_carry,curr_acc,curr_ir,sum)

BEGIN