Курсовая работа: Синтез схеми ПЛІС для інвертора

OR (curr_acc(1) AND curr_ir(1))

OR (curr_acc(0) AND curr_ir(0)));

WHEN SET_CARRY_OP =>

-- set the carry bit

next_acc <= curr_acc;-- ACC is not changed

next_carry <= '1';

next_zero <= curr_zero;-- zero flag is not changed

WHEN CLR_CARRY_OP =>

-- clear the carry bit

next_acc <= curr_acc;-- ACC is not changed

next_carry <= '0';

next_zero <= curr_zero;-- zero flag is not changed

WHEN OTHERS =>

-- don't do anything for undefined ALU opcodes

next_acc <= curr_acc;

next_carry <= curr_carry;

next_zero <= curr_zero;

END CASE;

END PROCESS;

-- this process describes the transitions of the GNOME state machine

-- and sets the control signals that are activated in each state

PROCESS(curr_st,curr_carry,curr_zero,curr_ir)

BEGIN

-- set the default values for these signals to avoid synthesis

-- of implied latches

sel_data_ram <= '0';

read <= '0';

write <= '0';

ld_ir <= '0';