Курсовая работа: Синтез схеми ПЛІС для інвертора

-- implied latches

sum <= "00000";

next_acc <= "0000";

next_carry <= '0';

next_zero <= '0';

CASE alu_op IS

WHEN ADD_OP =>

-- add the accumulator with the lower 4 bits of the IR and the carry

sum <= ('0' &amp; curr_acc) + ('0' &amp; curr_ir(3 DOWNTO 0))

+ ("0000" &amp; curr_carry);

next_acc <= sum(3 DOWNTO 0);-- ACC gets lower 4 bits of the sum

next_carry <= sum(4);-- carry is the most significant bit of the sum

next_zero <= curr_zero;-- zero flag is not changed

WHEN XOR_OP =>

-- XOR the accumulator with the lower 4 bits of the IR

next_acc <= curr_acc XOR curr_ir(3 DOWNTO 0);

next_carry <= curr_carry; -- carry flag is not changed

next_zero <= curr_zero; -- zero flag is not changed

WHEN PASS_OP =>

-- pass lower 4 bits of IR into ACC

next_acc <= curr_ir(3 DOWNTO 0);

next_carry <= curr_carry; -- carry flag is not changed

next_zero <= curr_zero; -- zero flag is not changed

WHEN AND_OP =>

-- test the ACC for zeroes in unmasked bit positions

next_acc <= curr_acc; -- ACC is not changed

next_carry <= curr_carry;-- carry is not changed

-- zero flag is set if ACC has zeroes where IR has ones

next_zero <= NOT( (curr_acc(3) AND curr_ir(3))

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