Курсовая работа: Синтез схеми ПЛІС для інвертора

inc_pc <= '0';

jump_pc <= '0';

alu_op <= "000";

CASE curr_st IS

WHEN FETCH =>

-- fetch an instruction from external RAM

sel_data_ram <= '0'; -- select the instruction RAM

read <= '1'; -- read from the RAM

ld_ir <= '1';-- load the instruction

-- register with the opcode

inc_pc <= '1'; -- increment the PC

-- to the next instruction

next_st <= DECODE; -- then decode the

-- instruction that was just loaded

WHEN DECODE =>

-- decode the instruction. Actually, this state is used to

-- read a direct-address operand from the data section of the

-- external RAM and store it in the lower 4 bits of the IR.

IF curr_ir(7 DOWNTO 4)=LOAD_DIR THEN

sel_data_ram <= '1';

read <= '1';

ld_ir_lsn <= '1';

END IF;

IF curr_ir(7 DOWNTO 4)=ADD_DIR THEN

sel_data_ram <= '1';

read <= '1';

ld_ir_lsn <= '1';

END IF;

IF curr_ir(7 DOWNTO 4)=XOR_DIR THEN