Курсовая работа: Синтез схеми ПЛІС для інвертора

-- read from RAM in the previous cycle and

END IF;

-- set the zero flag if all the bits are zero

next_st <= FETCH;

-- execution complete, so go fetch another instruction

WHEN others =>

END CASE;

END PROCESS;

-- this process makes the next value of all these signals into the

-- current value on the rising clock edge

PROCESS (clk,reset)

BEGIN

-- asynchronously reset the state of the GNOME microcomputer

IF reset='1' THEN

curr_st <= FETCH;-- start by fetching instructions

curr_pc <= "0000000";-- start at beginning of instruction RAM

curr_ir <= "00000000";

curr_acc <= "0000";-- clear accumulator

curr_carry <= '0'; -- clear carry flag

curr_zero <= '0'; -- clear zero flag

-- otherwise, update state on the rising clock edge

ELSIF (clk'event AND clk='1') THEN

curr_st <= next_st;

curr_pc <= next_pc;

curr_ir <= next_ir;

curr_acc <= next_acc;

curr_carry <= next_carry;

curr_zero <= next_zero;

END IF;