Курсовая работа: Синтез схеми ПЛІС для інвертора

acc_out: out std_logic_vector (3 downto 0)

);

end component;

component rom port (

sel_ram : in std_logic;

oe : in std_logic;

ADDR : in std_logic_vector (6 downto 0);

DATA : inout STD_LOGIC_VECTOR (7 downto 0));

end component;

component ram port

(clk : in std_logic;

sel_ram : in std_logic;

oe : in std_logic;

we : in std_logic;

address : in std_logic_vector(6 downto 0);

data : inout std_logic_vector(7 downto 0));

end component;

signal w_clk: std_logic;

signal w_reset: STD_LOGIC;

signal b_address: STD_LOGIC_VECTOR (6 DOWNTO 0);

signal b_data: STD_LOGIC_VECTOR (7 DOWNTO 0);

--signal w_csb: STD_LOGIC;-- active-low chip-select for external ROM/RAM

signal w_web: STD_LOGIC; -- active-low write-enable for external RAM

signal w_oeb: STD_LOGIC; -- active-low output-enable for external ROM/RAM

signal w_sel_ram: std_logic;

begin

oe_view <= w_oeb;

sel_ram_view <= w_sel_ram;

w_clk <= clk;