Курсовая работа: Синтез схеми ПЛІС для інвертора

data_view <= b_data;

addr_view <= b_address;

we_view <= w_web;

U1: gnome port map (

clk => w_clk,

reset => w_reset,

address =>b_address,

data => b_data,

--csb => w_csb,

web => w_web,

oeb => w_oeb,

sel_ram => w_sel_ram,

carry_out => carry_view,

pc_out => pc_view,

ir_out => ir_view,

acc_out => acc_view);

U2: rom port map (

sel_ram => w_sel_ram,

oe => w_oeb,

ADDR => b_address,

DATA => b_data);

U3: ram port map (

clk => w_clk,

sel_ram => w_sel_ram,

oe => w_oeb,

we => w_web,

address => b_address,

data => b_data);

end structural;