Курсовая работа: Устройство разделения цифрового потока данных

Q2 <= sreg64(2) after 1 ns ;

Q1 <= sreg64(1) after 1 ns ;

Q0 <= sreg64(0) after 1 ns ;

end v1 ;

-- D Flip Flop w asynchronous reset

library ieee ;

use ieee.std_logic_1164.all ;

entity DFFR is

port (RST : in std_logic ;

CLK : in std_logic ;

D : in std_logic ;

Q : out std_logic ;

QN : out std_logic

) ;

end DFFR ;

architecture v1 of DFFR is

signal n1 : std_logic ;

begin

process (RST,CLK)

begin

if RST = '1' then

n1 <= '0' after 1 ns ;

elsif (CLK'event and CLK='1') then

n1 <= D after 1 ns ;

end if ;

end process ;

Q <= n1 after 1 ns ;

QN <= not n1 after 1 ns ;

end v1 ;