Курсовая работа: Устройство разделения цифрового потока данных

Q2 <= sreg16(2) after 1 ns ;

Q1 <= sreg16(1) after 1 ns ;

Q0 <= sreg16(0) after 1 ns ;

end v1 ;

--32-bit Serial to Parallel Shift Register with asynchronous reset

library ieee ;

use ieee.std_logic_1164.all ;

entity SPREG32R is

port ( RST : in std_logic ;

CLK : in std_logic ;

SI : in std_logic ;

Q31,Q30,Q29,Q28,Q27,Q26,Q25,Q24 : out std_logic;

Q23,Q22,Q21,Q20,Q19,Q18,Q17,Q16 : out std_logic;

Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8 : out std_logic ;

Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 : out std_logic

) ;

end SPREG32R ;

architecture v1 of SPREG32R is

signal sreg32 : std_logic_vector (31 downto 0) ;

begin

process (RST,CLK)

begin

if RST = '1' then

sreg32 <= (others => '0') ;

elsif CLK = '1' and CLK'event then

sreg32 <= sreg32(30 downto 0) & SI ;

end if ;

end process ;

Q31 <= sreg32(31) after 1 ns ;