Курсовая работа: Устройство разделения цифрового потока данных

CLK : in std_logic ;

SI : in std_logic ;

Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8 : out std_logic ;

Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 : out std_logic

) ;

end SPREG16R ;

architecture v1 of SPREG16R is

signal sreg16 : std_logic_vector (15 downto 0) ;

begin

process (RST,CLK)

begin

if RST = '1' then

sreg16 <= (others => '0') ;

elsif CLK = '1' and CLK'event then

sreg16 <= sreg16(14 downto 0) & SI ;

end if ;

end process ;

Q15 <= sreg16(15) after 1 ns ;

Q14 <= sreg16(14) after 1 ns ;

Q13 <= sreg16(13) after 1 ns ;

Q12 <= sreg16(12) after 1 ns ;

Q11 <= sreg16(11) after 1 ns ;

Q10 <= sreg16(10) after 1 ns ;

Q9 <= sreg16(9) after 1 ns ;

Q8 <= sreg16(8) after 1 ns ;

Q7 <= sreg16(7) after 1 ns ;

Q6 <= sreg16(6) after 1 ns ;

Q5 <= sreg16(5) after 1 ns ;

Q4 <= sreg16(4) after 1 ns ;