Курсовая работа: Устройство разделения цифрового потока данных

end v1 ;

--64-bit Serial to Parallel Shift Register with asynchronous reset

library ieee ;

use ieee.std_logic_1164.all ;

entity SPREG64R is

port ( RST : in std_logic ;

CLK : in std_logic ;

SI : in std_logic ;

Q63,Q62,Q61,Q60,Q59,Q58,Q57,Q56 : out std_logic;

Q55,Q54,Q53,Q52,Q51,Q50,Q49,Q48 : out std_logic;

Q47,Q46,Q45,Q44,Q43,Q42,Q41,Q40 : out std_logic;

Q39,Q38,Q37,Q36,Q35,Q34,Q33,Q32 : out std_logic;

Q31,Q30,Q29,Q28,Q27,Q26,Q25,Q24 : out std_logic;

Q23,Q22,Q21,Q20,Q19,Q18,Q17,Q16 : out std_logic;

Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8 : out std_logic;

Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 : out std_logic

) ;

end SPREG64R ;

architecture v1 of SPREG64R is

signal sreg64 : std_logic_vector (63 downto 0) ;

begin

process (RST,CLK)

begin

if RST = '1' then

sreg64 <= (others => '0') ;

elsif CLK = '1' and CLK'event then

sreg64 <= sreg64(62 downto 0) & SI ;

end if ;

end process ;