Курсовая работа: Устройство разделения цифрового потока данных

library ieee ;

use ieee.std_logic_1164.all ;

entity NAND2 is

port (

IN1,IN0 : in std_logic ;

Z : out std_logic

) ;

end NAND2 ;

architecture v1 of NAND2 is

begin

Z <= not (IN1 and IN0) after 1 ns ;

end v1 ;

-- Inverter

library ieee ;

use ieee.std_logic_1164.all ;

entity INV is

port (

IN0 : in std_logic ;

Z : out std_logic

) ;

end INV ;

architecture v1 of INV is

begin

Z <= not IN0 after 1 ns ;

end v1 ;

-- Buffer

library ieee ;

use ieee.std_logic_1164.all ;

entity BUF is