Курсовая работа: Устройство разделения цифрового потока данных

IN0 : in std_logic ;

Z : out std_logic

) ;

end BUF ;

architecture v1 of BUF is

begin

Z <= IN0 after 1 ns ;

end v1 ;

-- 2-1 Multiplexer

library ieee ;

use ieee.std_logic_1164.all ;

entity MUX21 is

port (IN0,IN1,SEL : in std_logic ;

Z : out std_logic

) ;

end MUX21 ;

architecture v1 of MUX21 is

begin

Z <= IN0 after 1 ns when SEL = '0' else IN1 ;

end ;

-- 4-1 Multiplexer

library ieee ;

use ieee.std_logic_1164.all ;

entity MUX41 is

port (IN0,IN1,IN2,IN3,SEL0,SEL1 : in std_logic ;

Z : out std_logic

) ;

end MUX41 ;

architecture v1 of MUX41 is