Курсовая работа: Устройство разделения цифрового потока данных

port (

IN0 : in std_logic ;

Z : out std_logic

) ;

end component ;

component MUX41

port (IN0,IN1,IN2,IN3,SEL0,SEL1 : in std_logic ;

Z : out std_logic

) ;

end component ;

signal nLRCLK, pLRCLK, nSCLK, pSCLK, nSDATA, pSDATA : std_logic;

signal i24b, i20b, i18b, i16b : std_logic;

signal RESET, iDOL, iDOR, iCLK, iLE : std_logic;

begin

RSTI: INV port map (IN0 => RST, Z => RESET);

DD1A: INV port map (IN0 => SCLK, Z => nSCLK);

DD1D: INV port map (IN0=> nSCLK, Z => pSCLK);

DD1B: INV port map (IN0 => SDATA, Z => nSDATA);

DD1E: INV port map (IN0 => nSDATA, Z => pSDATA);

DD1C: INV port map (IN0 => LRCLK, Z => nLRCLK);

DD1F: INV port map (IN0 => nLRCLK, Z => pLRCLK);

CLKB: BUF port map (IN0 => nSCLK, Z => iCLK);

DD2: SPREG16R port map (RST => RESET, CLK => pSCLK, SI => pSDATA,

Q7 => i24b, Q11 => i20b, Q13 => i18b, Q15 => i16b);

DDMX: MUX41 port map (IN0 => i24b, IN1 => i20b, IN2 => i18b, IN3 => i16b,

SEL0 => RL0, SEL1 => RL1, Z => iDOR);

DD4: DFFR port map (RST => RESET, D => pLRCLK, CLK => pSCLK, Q => iLE);

DD5: SPREG32R port map (RST => RESET, CLK => pSCLK, SI => iDOR,

Q31 => iDOL);