Курсовая работа: Устройство разделения цифрового потока данных

--Test signal generator for DS1851

library ieee ;

use ieee.std_logic_1164.all ;

entity Tester1851 is

port (

CLK : in std_logic

);

end Tester1851;

architecture v1 of Tester1851 is

component TS1851

port (

RST : out std_logic;

SCLK : in std_logic;

SDATA : out std_logic;

LRCLK : out std_logic

);

end component ;

component DS1851

port (

RST : in std_logic;

SCLK : in std_logic;

SDATA : in std_logic;

LRCLK : in std_logic;

RL1 : in std_logic;

RL0 : in std_logic;

LE : out std_logic;

CLK : out std_logic;

DOL : out std_logic;

DOR : out std_logic