Курсовая работа: Устройство разделения цифрового потока данных

wait on SCLK until SCLK='0';

DSReg <= RD2;

wait for 10ns;

LRCLK <= '1';

SDATA <= DSReg(31);

RD2L: for i in 30 downto 0 loop

wait on SCLK until SCLK='0';

DSReg <= DSReg(30 downto 0) & '0';

wait for 10ns;

SDATA <= DSReg(31);

end loop RD2L;

wait on SCLK until SCLK='0';

DSReg <= LD3;

wait for 10ns;

LRCLK <= '0';

SDATA <= DSReg(31);

LD3L: for i in 30 downto 0 loop

wait on SCLK until SCLK='0';

DSReg <= DSReg(30 downto 0) & '0';

wait for 10ns;

SDATA <= DSReg(31);

end loop LD3L;

wait on SCLK until SCLK='0';

DSReg <= RD3;

wait for 10ns;

LRCLK <= '1';

SDATA <= DSReg(31);

RD3L: for i in 30 downto 0 loop

wait on SCLK until SCLK='0';