Курсовая работа: Устройство разделения цифрового потока данных

RST : in std_logic;

BCLK : in std_logic;

SDATA : in std_logic;

LRCLK : in std_logic;

MCLK : in std_logic;

BCLK_O : out std_logic;

LRCLK_O : out std_logic;

SDATA_L : out std_logic;

SDATA_R : out std_logic;

MCLK_O : out std_logic

);

end component ;

component BUF

port (

IN0 : in std_logic ;

Z : out std_logic

) ;

end component ;

signal BCLK, SDATA, LRCLK, RST : std_logic;

signal LD1, LD2, LD3, RD1, RD2, RD3, DSReg : std_logic_vector (31 downto 0);

begin

D0: BUF port map (IN0 => CLK, Z => BCLK);

D2: DS1853 port map (RST => RST, BCLK => BCLK,

SDATA => SDATA, LRCLK => LRCLK,

MCLK => BCLK);

Test: process

begin

LD1 <= "01100110000000011000000000000000";

RD1 <= "01111000000001111000000000000000";