Курсовая работа: Устройство разделения цифрового потока данных

wait for 10ns;

SDATA <= DSReg(31);

end loop RD3L;

wait on SCLK until SCLK='0';

DSReg <= LD1;

wait for 10ns;

LRCLK <= '0';

wait;

end process;

end v1;

--Tester1853.vhd

--Test signal generator for DS1853

library ieee ;

use ieee.std_logic_1164.all ;

entity Tester1853 is

port (

CLK : in std_logic

);

end Tester1853;

architecture v1 of Tester1853 is

component TS1853

port (

RST : out std_logic;

SCLK : in std_logic;

SDATA : out std_logic;

LRCLK : out std_logic

);

end component ;

component DS1853