Курсовая работа: Устройство разделения цифрового потока данных

LRCLK <= '0';

SDATA <= DSReg(31);

LD1L: for i in 30 downto 0 loop

wait on SCLK until SCLK='0';

DSReg <= DSReg(30 downto 0) & '0';

wait for 10ns;

SDATA <= DSReg(31);

end loop LD1L;

wait on SCLK until SCLK='0';

DSReg <= RD1;

wait for 10ns;

LRCLK <= '1';

SDATA <= DSReg(31);

RD1L: for i in 30 downto 0 loop

wait on SCLK until SCLK='0';

DSReg <= DSReg(30 downto 0) & '0';

wait for 10ns;

SDATA <= DSReg(31);

end loop RD1L;

wait on SCLK until SCLK='0';

DSReg <= LD2;

wait for 10ns;

LRCLK <= '0';

SDATA <= DSReg(31);

LD2L: for i in 30 downto 0 loop

wait on SCLK until SCLK='0';

DSReg <= DSReg(30 downto 0) & '0';

wait for 10ns;

SDATA <= DSReg(31);