Курсовая работа: Устройство разделения цифрового потока данных

end component ;

component BUF

port (

IN0 : in std_logic ;

Z : out std_logic

) ;

end component ;

signal SCLK, SDATA, LRCLK, RST : std_logic;

signal LD1, LD2, LD3, RD1, RD2, RD3, DSReg : std_logic_vector (31 downto 0);

begin

D0: BUF port map (IN0 => CLK, Z => SCLK);

D2: DS1851 port map (RST => RST, SCLK => SCLK,

SDATA => SDATA, LRCLK => LRCLK,

RL1 => '1', RL0 => '1');

Test: process

begin

LD1 <= "01100110000000011000000000000000";

RD1 <= "01111000000001111000000000000000";

LD2 <= "01100110000111111000000000000000";

RD2 <= "01111000011111111000000000000000";

LD3 <= "01100111111111111000000000000000";

RD3 <= "01111111111111111000000000000000";

SDATA <= '0';

LRCLK <= '1';

RST <= '0';

wait for 50ns;

RST <= '1';

wait on SCLK until SCLK='0';

DSReg <= LD1;