Курсовая работа: Устройство разделения цифрового потока данных

BUFC: BUF port map (IN0 => iCLK, Z => CLK);

BUFL: BUF port map (IN0 => iDOL, Z => DOL);

BUFR: BUF port map (IN0 => iDOR, Z => DOR);

end v1 ;

--DS1853.vhd

--Data Separator for AD1852/AD1853 delta-sigma DAC

library ieee ;

use ieee.std_logic_1164.all ;

entity DS1853 is

port (

RST : in std_logic;

BCLK : in std_logic;

SDATA : in std_logic;

LRCLK : in std_logic;

MCLK : in std_logic;

BCLK_O : out std_logic;

LRCLK_O : out std_logic;

SDATA_L : out std_logic;

SDATA_R : out std_logic;

MCLK_O : out std_logic

);

end DS1853;

architecture v1 of DS1853 is

component SPREG64R

port ( RST : in std_logic ;

CLK : in std_logic ;

SI : in std_logic ;

Q63,Q62,Q61,Q60,Q59,Q58,Q57,Q56 : out std_logic;

Q55,Q54,Q53,Q52,Q51,Q50,Q49,Q48 : out std_logic;